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  • Amandtec - Tuesday, September 25, 2018 - link

    Remarkable. CPU cores now make less than 3% of the silicon. Who would have thought it...
  • mkozakewich - Tuesday, September 25, 2018 - link

    That's each core. Obviously the whole CPU, caches included, are closer to 21% of the die.
  • solipsism - Tuesday, September 25, 2018 - link

    You're right, mkozakewich. I just added up the values for the total die size and it didn't even come close to matching, but it works out when you multiply the number of each core type. Too bad they don't like you edit. 🤦‍♂️
  • Wilco1 - Tuesday, September 25, 2018 - link

    The CPUs with L2 are 14%. The system cache is around 6mm^2, so adds another 7%. However the system cache might not be exclusive to the CPUs.

    Also impressive is 7nm achieved density at 82.9 million transistors/mm^2 - quite close to theoretical density of ~100 mt/mm^2.
  • tipoo - Tuesday, September 25, 2018 - link



    iirc it was part of how they addressed the bandwidth on the phone parts (which have half the memory bit width of the X parts) for the GPU, so the GPU definitely has access.
  • solipsism - Tuesday, September 25, 2018 - link

    My calculations come out to slightly over 3%: 100 * ((2.07 + 0.43) / 83.27) = 3.0022817341%

    But I don't think that's unusual since this isn't just a CPU, but an SoC with the RAM, GPU, and large CPU complex (which I assume is where the neural engine resides ¯\_(ツ)_/¯).

    I wonder how much the 2 cores take up on something like an Apple Watch since that's an SiP.
  • solipsism - Tuesday, September 25, 2018 - link

    Correction: Just the cores are: (((2.07 × 2 big cores) + (0.43 × 4 small cores)) / 83.27) × 100 = 7.0373483848%.

    Also, it looks like they simply didn't include the neural processing unit in their chart even though I thought the A11 included one last year.
  • name99 - Tuesday, September 25, 2018 - link

    Apple Watch also has GPU and NPU.
    (The most obvious way to do that would be to assume it gets 1/8 of the A12 NPU complex -- OK, and 1/4 of the GPU complex -- which seems overkill...)
    It's still unclear quite how this was handled. Perhaps there's a "natural" way to slice a single Apple GPU core in two?

    And of course the two cores on Apple Watch are Tempest cores (the small cores).
  • DanNeely - Tuesday, September 25, 2018 - link

    CPU cores have been a minority of the die area on most consumer facing CPUs for a long time. For complex SoC's this has always been the case because you've got so many not-CPU things packed in. It's also been the case in the PC world since the CPU ate the north bridge and brought the dram controllers and IGPU onboard. GPUless server processors might be an exception, although I wouldn't be surprised if they ended up more cache than compute.
  • dand2 - Tuesday, September 25, 2018 - link

    How did you modify the die image colors like that?
  • PeachNCream - Tuesday, September 25, 2018 - link

    Photoshop.

    Or GIMP if you like to torture yourself with a terrible UI because you want to save money more than you want to save your own sanity.
  • qlum - Tuesday, September 25, 2018 - link

    I think the gimp ui is fine it just follows a different logic than Photoshop so coming from Photoshop it will be terrible, Whenever I try to use any adobe program I get the same feeling.

    I will not deny that photoshop is a bit more capable than gimp but it does the job and for home use if you don't want to pirate gimp + inkscape is a great option.
  • qlum - Tuesday, September 25, 2018 - link

    I will add though that you should configure extra shortkeys as those are a bit lacking by default.
  • PeachNCream - Tuesday, September 25, 2018 - link

    I was joking about GIMP. It's my preferred image editor and the only viable option under Linux.
  • solipsism - Tuesday, September 25, 2018 - link

    "Stay tuned for our full iPhone XS and XS Max review in the near term future."

    :snoopy dance: considering the in-depth iPhone X review never materialized.
  • iamlilysdad - Tuesday, September 25, 2018 - link

    Quite a few phones that should be reviewed aren't reviewed. It's disappointing. I always looked forward to Anandtech phone reviews for their objectivity and thoroughness.
  • Ian Cutress - Tuesday, September 25, 2018 - link

    We didn't have a Senior Smartphone Editor for about a year.
  • erotomania - Wednesday, September 26, 2018 - link

    Boo fkn' hoo
  • solipsism - Tuesday, September 25, 2018 - link

    I also love their in-depth reviews. Because of how thorough they were I never minded that it could take a couple months to post.
  • iwod - Tuesday, September 25, 2018 - link

    What are the rest of those space? ISP, NAND Controller, Video Encoder, Decoder, Security Enclave, what else?

    And what is System Cache? L3 SRAM?
  • Andrei Frumusanu - Tuesday, September 25, 2018 - link

    It's a SoC wide cache level.
  • name99 - Tuesday, September 25, 2018 - link

    Each of those separate blocks has a 64-bit controller CPU called Chinook. Chinook is a type of (non-vortex) wind, which suggests that it's from the Zephyr/Mistral/Tempest family. Examinations of the code that these run (firmware BLOBs in iOS12 that are presumably things like initialization and power management --- and at least some aspects of scheduling for the GPU) reveal FP instructions but no NEON, so they may be something like a Tempest or Zephyr with NEON stripped down to minimal FP.

    There's also an FPGA on the SoC. This Lattice FPGA has been there since the A7 and we still don't know how it's used. And there's also the M12 (motion coprocessor) which I expect has some tiny ARM core on it. (Maybe Apple now designs those, or maybe it's still vanilla ARM.)
  • skavi - Thursday, September 27, 2018 - link

    Hey, you seem knowledgeable about this stuff. I have a really dumb question that I've never known where to ask: what's in the unlabeled area of SoCs? I know with Android there's typically a modem there, but what fills the rest of the space? Thanks!
  • name99 - Thursday, September 27, 2018 - link

    There's LOTS of stuff, some known, some not. Includes
    - Secure enclave (separate core, separate storage)
    - ISP (camera processing)
    - media encoder/decoder (video and audio)
    - M12 (motion coprocessor, detects acceleration and rotation, provides orientation info for AR, supports raise to wake and [I think] "Hey Siri" functionality, ie always listening for that phrase even when screen is dark
    - flash controller (and a few other small IO controllers).

    + The big IO (cell, wifi, BT, GPS) is still off chip. Apple has enough know-how now to create W3 (WiFi and BT) but W3 WiFi is still way behind state of the art (no MIMO, just 2.4GHz, very much bare minimum to solve certain tasks and no more).

    - There's also known to be a Lattice FPGA on the SoC (one has been there since the A7), but as far as I know we STILL don't know how it's used...
  • qzy__ - Tuesday, September 25, 2018 - link

    It seems that A11 has 3MB private L2 each Monsoon core. Also, it has 2MB L2 which 4 Mistral small cores shared with, but it is likely that the two big cores can access all 8M L2 simultaneously. I'm looking forward you can analyse how the L2 cache one the A12 chip works.
  • Tigran - Tuesday, September 25, 2018 - link

    Andrei, could you please make clear - is GPU (14.88) also incl. cores, like CPU? And what about NPU - no figures?
  • ikjadoon - Tuesday, September 25, 2018 - link

    >Therefor I did my own analysis and took the liberty of adding a bit more visibility and custom labelling of the die shot

    I think "therefore" is the one wanted, not "therefor". "Therefor" means "for it", but "therefore" is a conjunction meaning "as a result".

    https://www.grammarly.com/blog/therefore-vs-theref...
  • porcupineLTD - Tuesday, September 25, 2018 - link

    Thank you for the insightful contribution, this site would be nothing without comments like yours!
  • pukemon1976 - Tuesday, September 25, 2018 - link

    why don't you apply to anandtech?
  • damianrobertjones - Wednesday, September 26, 2018 - link

    Cool. It's great to learn. Thank you!
  • eastcoast_pete - Tuesday, September 25, 2018 - link

    Thanks Andrei! I look forward to your full review (deep dive? that'd be great) of the A12. I hadn't realized that the A12's NPU would be that big; the NPUs seem to take up as much area as the 4 big cores, if not more. I am curious to learn how iOS and various Apple apps put all that silicon dedicated to the NPU to (good?) use.
    Showing my ignorance here: Is Apple combining DSP functions and neuronal processing and are calling it their NPU, or is there a separate DSP block on the A12 that is simply not labelled as such here?
  • Zoolook - Wednesday, September 26, 2018 - link

    The A12 has 2 big cores, not 4.
  • eastcoast_pete - Wednesday, September 26, 2018 - link

    Yes, typo. Still the NPU area is as large as or larger than the two vortex cores. Also, any idea about where the DSP circuitry lives on the A12? Are they taken care of by the "NPU" blocks, or just not identified on the die shot?
  • Andrei Frumusanu - Wednesday, September 26, 2018 - link

    Or there simply isn't one.

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