Intel has recently updated its developer documentation for instruction set extensions, and in the process has disclosed information on both new instructions for and the codename of its next-generation low-power processor microarchitecture. Dubbed "Tremont", the forthcoming processor core look to replace Goldmont Plus in the upcoming Atom, Celeron, and Pentium Silver-branded SoCs.

According to the Intel Architecture Instruction Set Extensions (ISE) and Future Features Programming Reference document, the Goldmont Plus microarchitecture will not be the end of the road for Intel’s low-cost/low-power cores. In the coming years it will be succeeded by the codenamed Tremont microarchitecture and its successors. On the manufacturing side of matters, nothing has officially been disclosed, but right now our suspicion is that processors based on the Tremont will be made using the company’s 10 nm process technology. To date we haven't seen Intel use their enhanced “+” and “++” 14nm process technologies to make SoCs for entry-level and energy-efficient PCs - as the original 14nm provides better density - so it seems unlikely that Intel would start now.

A key question about the Tremont is what architecturaly improvements it will bring. While Intel's document does specify the new instructions, it doesn't offer any general architectural insight. Intel's general trend thus far since Silvermont has been to gradually widen their out-of-order execution design, starting with two-way, moving to three-way (Goldmont), and then to a three-way front-end plus a four-way allocation and retirement backend. So it may be that we see Intel go this route, as they already have a number of tricks left in their bag from Core, and it meshes well with the high density aspects of their 10nm processes, which favors more complex processors.

As for the ISE improvements, Intel’s Tremont will feature CLWB, GFNI (SSE-based), ENCLV, and Split Lock Detection instruction set extensions, which are also set to arrive with Intel’s Ice Lake processors. Also set to arrive with Tremont will be CLDEMOTE, direct store, and user wait instructions (see details in the table below). Unlike the earlier instructions, these are unique to Tremont and are not scheduled to be supported by the Ice Lake (or other documented Intel’s cores).

New Instruction Set Extensions of Goldmont Plus and Tremont CPUs
  Instruction Purpose Description
Goldmont Plus PTWRITE

Write Data to a Processor Trace Packet
Debugging Unclear.

User-Mode Instruction Prevention
Security Prevents execution of certain instructions if the Current Privilege Level (CPL) is greater than 0. If these instructions were executed while in CPL > 0, user space applications could have access to system-wide settings such as the global and local descriptor tables, the task register and the interrupt descriptor table.

Read Processor ID
General Quickly reads processor ID to discover its feature set and apply optimizations/use specific code path if possible.
Tremont CLWB

Cache Line
Write Back
Performance Writes back modified data of a cache line similar to CLFLUSHOPT, but avoids invalidating the line from the cache (and instead transitions the line to non-modified state). CLWB attempts to minimize the compulsory cache miss if the same data is accessed temporally after the line is flushed if the same data is accessed temporally after the line is flushed.
GFNI (SSE) Security SSE-based acceleration of Galois Field Affine Transformation alghorithms.
ENCLV Security Further enhancement of SGX version 1 capabilities.
CLDEMOTE Performance Enables CPU to demote a cache line with a specific adress from the nearest cache to a more distant cache without writing back to memory. Speeds up access to this line by other cores within a CPU.
Direct stores: MOVDIRI, MOVDIR64B Performance  
User wait: TPAUSE, UMONITOR, UMWAIT Power Direct CPU to enter certain stages before an event happens.
Split Lock Detection    
Source: Intel Architecture Instruction Set Extensions and Future Features Programming Reference (pages 12 and 13)

The fact that Intel is readying its “Future Tremont and later” microarchitectures reveals that even after the company withdrew from smartphone SoCs, it sees plenty of applications that could use its low-power/low-cost Atom cores. There is sitll a notable market for budget PCs as well as embedded and semi-embeded markets for items like IoT edge devices, all of which Intel intends to continue serving with the line of smaller, cheaper cores. Meanwhile, consistent ILP and performance improvements as well as introduction of new ISEs to these microarchitectures show that Intel wants these cores to offer competitive performance to other low-cost processors, while still maintaining near feature set parity to Intel's high-performance cores.

Related Reading

Sources: Intel, WikiChip

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  • rojer_31 - Tuesday, April 24, 2018 - link

    Care to share the laptop model?
  • Azurael - Tuesday, April 24, 2018 - link

    Core-M (Y/U) parts are SoCs too, albeit MCM, so nothing gained there....
  • Morawka - Monday, April 23, 2018 - link

    Intel still unwilling to sell their Core architecture for under $100, thus they extend the life of Atom.
  • MrSpadge - Tuesday, April 24, 2018 - link

    Yeah, sure:
    Celeron G3900 starts at 27€
    Pentium Gold G4560 starts at 44€
  • yhselp - Wednesday, April 25, 2018 - link

    To be honest, and just to clarify, I've never been prejudiced against Atom, even back in the netbook age and the single-core in-order models, the EeeBook I had worked okay on XP and was as expected, I took AnandTech's word on N3450 being okay and acceptable based on the Chuwi LapBook 14.1 review, and bought a Chuwi Hi13 with the same N3450 without doing additional research, and it turned out to be a massive disappointment in terms of performance. Perhaps it's because of the resolution of the screen, which is three times higher, but still - it's so cripplingly slow that's it's far, far from acceptable, and I barely use it because of that, and it wasn't that cheap either. So if Atom is to be a viable, albeit low-end, alternative, it definitely needs more, or my experience if because of the high-res screen.
  • mode_13h - Thursday, April 26, 2018 - link

    I'll bet it uses a single-channel DRAM configuration.
  • mode_13h - Monday, April 23, 2018 - link

    On a more serious note, the cache control extensions are overdue.

    I have been wanting CLWB (among other things) in x86, for more than a decade. It's useful when you modify some long-lived datastructure that you're not going to touch again (but might still read), for a long while. So you tell the CPU: "go ahead and write this out". There's nothing to be gained by deferring the write, and doing it now could reduce latency on the next cache miss in that set.

    CLDEMOTE is a similar idea, but for shared data structures you know are going to be accessed by other threads. By proactively demoting it, you're reducing the time a thread running on another core will stall on it.

    Another extension I wish they'd add is a pre-write instruction that allocates cache lines for a specified address range. That could let you avoid a fetch on write miss, when you're just going to overwrite the whole darn thing. For security reasons, the CPU would probably first have to zero it.
  • Elstar - Monday, April 23, 2018 - link

    I wonder if any of the new Atoms will get a longer pipeline, or is that a premium feature reserved for the Core/Xeon line?
  • StevoLincolnite - Monday, April 23, 2018 - link

    I am hoping to see a 6-core Atom, would like to see Hex-core chips as the minimum going forward.

    Would be great in a low-powered 2-in-1 device for $300 or less.
  • DanNeely - Monday, April 23, 2018 - link

    Unless they adopt something big.LITTLEesque I'd hope not. A 6 core atom makes as little sense as an 8 core A5x SoC ever has.

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