DualDDR Memory Architecture

The reason that the original nForce was able to offer such compelling integrated graphics performance was because of its dual channel DDR memory controller. Even with DDR400 memory, a 64-bit DDR bus would only be able to offer 3.2GB/s of memory bandwidth, thus going to dual 64-bit memory channels makes a lot of sense.

We’ve proved in the past that the dual channel memory architecture, which NVIDIA is now calling DualDDR, only provides a performance improvement in 3D games with integrated graphics enabled. The reason that adding more memory bandwidth doesn’t improve overall system performance is because the Athlon XP’s FSB is stuck at 133MHz offering up to 2.1GB/s of bandwidth between the Athlon XP and the nForce2 IGP/SPP. With a maximum of 2.1GB/s of data going between the CPU and the IGP/SPP, having twice or even three times that bandwidth between the IGP/SPP and main memory is useless without a memory bandwidth hungry device eating up the remaining bandwidth.

With most I/O taking up less than 100MB/s of bandwidth and audio even less than that, any memory bandwidth offered above and beyond that initial 2.1GB/s goes to waste without integrated graphics enabled. Enabling integrated graphics changes the picture significantly, as we already know that even the 10.4GB/s of bandwidth that the GeForce4 Ti 4600 is allocated isn’t enough at higher resolutions.

The DualDDR setup works identically to TwinBank on the original nForce chipset; with only one DIMM installed, the chipset turns off one of the two 64-bit memory controllers. With a second or third installed, the nForce2 IGP/SPP will enable both memory controllers; and just like the original nForce, you will be able to install DIMMs of different sizes.

If you install two DIMMs, a 128MB and 256MB module then only the first 256MB (smallest memory module size X number of memory modules installed) of memory will be accessible using both 64-bit memory controllers; any memory accessed above 256MB will only be accessed using a single 64-bit channel. The chipset supports up to 3GB of memory and can support 1GB DIMMs in each of its three sockets although stability will be up to the motherboard manufacturers to ensure.

The DualDDR memory controllers in the nForce2 IGP/SPP support DDR266, 333 and 400 modules. Support for DDR333 and DDR400 really only matters, once again, when integrated graphics is enabled. NVIDIA’s own internal testing has also revealed that when the FSB and memory buses are operating synchronously (i.e. both running at 133MHz DDR), the nForce2 is in its fastest state. This makes perfect sense seeing as how the additional memory bandwidth is pretty much useless to the CPU but it isn’t what we’ve seen from VIA for example with the KT333.

VIA’s KT333 chipset is faster with DDR333 SDRAM than it is with DDR266, although according to NVIDIA the nForce2 running at 266/266 (133MHz DDR FSB and memory bus) is faster than the KT333 running at 266/333 or 266/266. NVIDIA’s approach to this involves using DDR333 but running it synchronously with the FSB and taking advantage of the faster memory by using more aggressive memory timings. We’ve hypothesized that the reason the KT333 runs faster with DDR333 SDRAM is because VIA tuned their memory controller for DDR333 operation while not bothering with optimizing DDR266 performance; given that VIA expects DDR333 to become the memory of choice by the end of this year, this isn’t too far fetched.

To sum things up, if you’re not running with integrated graphics enabled then using DDR333 memory but running it at DDR266 speeds with tighter timings will yield the highest performance on nForce2 according to NVIDIA. With integrated graphics enabled, the highest bandwidth configuration (see table above) will yield the highest performance in 3D applications.

Despite NVIDIA’s assertion that synchronous bus clocking offers the absolute highest performance levels, NVIDIA let us know that end users will be able to asynchronously select FSB, memory and AGP operating frequencies. While this is obviously up to motherboard manufacturer implementations, the potential for independent 1MHz clock increments for each of the aforementioned buses is possible. The biggest benefit this offers is the ability to run the AGP clock within specification while overclocking both the FSB and memory bus.

A new IGP and introducing the SPP Dynamic Adaptive Speculative Pre-Processor – Take 2
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