Last Thursday in its annual Investor Meeting Intel revealed the first details of its 3D NAND technology and announced that it will begin the shipments of 3D NAND in the second half of 2015. While Intel's investment in 3D NAND hasn't been a secret, the company has been relatively quiet about any specifics and the vital specs such as the number of layers and die capacity have remained unknown. In Thursday's webcast, Rob Crooke, Senior VP and General Manager of Intel's non-volatile memory group, disclosed that Intel's first generation 3D MLC NAND die will be 256Gbit (32GB) in capacity and will consist of 32 layers. The technology also enables a 384Gbit (48GB) TLC (3-bit-per-cell) die as we have learned over the years.

Intel claims that its 3D NAND is the most cost effective on the market and bases this on the fact that its die is 256Gbit whereas Samsung's is only up to 128Gbit at the moment. I'm not sure if I buy Intel's claim because while it's true that a higher capacity die results in higher array efficiency (i.e. peripheral circuitry takes less area), Samsung consciously went from a 24-layer 128Gbit MLC die to a 32-layer 86Gbit MLC die. In other words, Samsung could have upped the die capacity to ~170Gbit by just adding the extra layers, but the company chose to go with a smaller die instead. Smaller capacity dies have advantages in performance (higher parallelism) and applicability because eMMC/microSD devices have very strict die size constraints, so that might be a part of the reason why Samsung's strategy is so different from Intel's and Micron's. 

NAND Die Size

As the graph above shows, Intel's/Micron's NAND dies have historically been larger than the competitors', so the die capacity alone isn't enough to dictate whether Intel's 3D NAND is more cost efficient than Samsung, especially because both have 32 layers. Unlike Samsung, Intel didn't reveal the lithography that is used to manufacture the 3D NAND, but I would say it's safe to assume that the lithography is in the order of 30nm or 40nm because the whole idea of 3D NAND is to move away from multi-patterning to cut costs and with today's technology the smallest pitch of single-patterning is somewhere between 30nm and 40nm. Either way, it will be very interesting to see how Intel's 3D NAND stacks up against Samsung's because there are also some structural differences that affect the production cost as well as performance and endurance, but I'll save the structural analysis for a future article.

Intel said that 3D NAND technology will enable +10TB SSDs in the 'next couple of years', but it wasn't clear whether that is with first generation 3D NAND or some later generation with more layers and higher die capacity. Currently Intel's lineup tops out at 2TB (P3700 & P3600) with a 128Gbit die, so the 256Gbit die alone isn't enough to bring the capacities above 10TB. With effective controller development it should certainly be possible to build a 10TB SSD with a 256Gbit die, although I'm still inclined to believe that Mr. Crooke was referring to second or third generation 3D NAND with his statement. 

Similar to Intel's previous NAND efforts, 3D NAND has been jointly developed with Micron and will most likely be manufactured in the co-owned Utah plant as Intel sold its share in other fabs a couple of years ago. Interestingly enough, Mr. Crooke said that they also have the ability to bring 3D NAND production to an Intel fab, although to me that sounded more like a statement of technological possibility rather than a hint of future strategy. I wouldn't rule it out, though, but like Mr. Crooke said in the Q&A, Intel needs to have significant competitive advantage for it to make sense. In the past Intel's NAND technologies have generally been slightly ahead of the rest of the industry, but at least as of now Intel doesn't seem to have any substantial advantage in 3D NAND technology as Samsung is already shipping a 32-layer die and will likely ship a 48-layer die before Intel ships its 32-layer product.

All in all, we'll likely get more crumbs of information as the second half of 2015 gets closer. Given Intel's recent SSD strategy, I expect 3D NAND to first find its way to enterprise-class SSDs, but we'll see soon enough.

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  • Laststop311 - Wednesday, November 26, 2014 - link

    The reason there was an aggressive push to smaller nodes is because without stacking the only way you can increase density is by going smaller cells. Now that they can stack they can use cheaper single patterning and still keep high densities.
  • Laststop311 - Wednesday, November 26, 2014 - link

    Well smaller cells or increasing the overall die size but increasing the die size is an expensive poor option so they pushed smaller and smaller nodes on 2d nand to increase the max capacity. Even though manufacturing at the smaller nodes was more expensive it was still cheaper than pushing up the density any other way. Now they can cut manufacturing costs down using single pattern litho cells and still have nice 1TB size with 2TB already possible and right around the corner. I'm sure we will see consumer 2TB SSD's by the end of 2015.

    Also since they are back to 40nm cell size write endurance is right back through the roof too. 40nm MLC is incredibly durable compared to the tiny 1xnm companies are using now. With 40nm even when samsung switches to TLC it will have more endurance than the 16nm and 19nm MLC nand. With 34nm or 40nm 32 layer stacking + 3 bit per cell and new controllers that can handle it, 4TB ssd's will become affordable. There is no point to go to more expensive double and triple patterning litho when we will already be able to get 4TB ssd's at the larger cell sizes with better endurance. Maybe for the 10TB intel is talking about.
  • sonicmerlin - Wednesday, November 26, 2014 - link

    Uh... Die size is also a major cost, as well as the number of layers. A smaller node lets you use smaller dies and significantly reduce the number of layers.

    Right now I think there are so few companies with the 3D NAND tech that no one wants to rock the price boat yet.
  • Laststop311 - Wednesday, November 26, 2014 - link

    im sure they did a cost comparison of what would cost them more. Using a larger die and more layers with single patterning litho or using smaller die and less layers with double or triple pattern litho. Defect rates go up with the smaller litho as more steps = more chances for defects. I'm sure they did the math and chose the best mix of characteristics to give them the lowest manufacturing costs. If 20nm was cheaper they would of done it I'm sure and charged the same price and pocketed an even higher percentage of net profit.

    Do you really think they would just decide to use a process that cost them more money and make less profit on purpose? When 20nm v nand becomes the cheapest option then they will do it. If this EUV tech would get figured out than they could single pattern 20nm with it and leap frog 20nm into the cheap sweet spot.
  • DerekZ06 - Thursday, December 4, 2014 - link

    >Do you really think they would just decide to use a process that cost them more money and make less profit on purpose?

    Companies Compete.
  • cointelpro123 - Wednesday, November 26, 2014 - link

    Why do these companies scrap their old production that is builtup and efficient?

    Intel and other companies can have two sections one from the new production process and use the older process for additional memory.

    Let say Intel was going to introduce 512GB only of this 3D memory. They can have 512GB plus 1TB of the older production process. The benchmarks can test the new interface for speed.
  • Rockfella.Killswitch - Thursday, November 27, 2014 - link

    Will it be better than Samsung 850 Pro's 3D nand drives? I just bought the 128GB yesterday.
  • earl colby pottinger - Saturday, December 6, 2014 - link

    That is weird because I bought a 240GB drive on Black Friday for $109 and note that was in Canadian dollars which I think were worth $0.88 American at the time.

    It is in the computer I am using right now!

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