An executive visiting various research divisions across the globe isn’t necessarily new, but with a focus on social media driving named individuals at each company to keep their followers sitting on the edge of their seats means that we get a lot more insights into how these companies operate. The downside of posting to social media is when certain images exposing unreleased information are not vetted by PR or legal, and we get a glimpse into the next generation of technology. That is what happened today.

EVP and GM of Intel’s Client Computing Group, Gregory Bryant, is this week spending some time at Intel’s Israel R&D facilities in his first overseas Intel trip in of 2021. An early post on Sunday morning, showcasing Bryant’s trip to the gym to overcome jetlag, was followed by another later in the day with Bryant being shown the offices and the research. The post contained four photos, but was rapidly deleted and replaced by a photo with three (in the tweet above). The photo removed showcases some new information about next-generation Thunderbolt technology.

In this image we can see a poster on the wall showcasing ‘80G PHY Technology’, which means that Intel is working on a physical layer (PHY) for 80 Gbps connections. Off the bat this is double the bandwidth of Thunderbolt 4, which runs at 40 Gbps.

The second line confirms that this is ‘USB 80G is targeted to support the existing USB-C ecosystem’, which follows along that Intel is aiming to maintain the USB-C connector but double the effective bandwidth.

The third line is actually where it gets technically interesting. ‘The PHY will be based on novel PAM-3 modulation technology’. This is talking about how the 0 and 1s are transmitted – traditionally we talk about NRZ encoding, which just allows for a 0 or a 1 to be transmitted, or a single bit. The natural progression is a scheme allowing two bits to be transferred, and this is called PAM-4 (Pulse Amplitude Modulation), with the 4 being the demarcation for how many different variants two bits could be seen (either as 00, 01, 10, or 11). PAM-4, at the same frequency, thus has 2x the bandwidth of an NRZ connection.

So what on earth in PAM-3?

From Teledyne LeCroy on YouTube

PAM-3 is a technology where the data line can carry either a -1, a 0, or a +1. What the system does is actually combine two PAM-3 transmits into a 3-bit data signal, such as 000 is an -1 followed by a -1. This gets complex, so here is a table:

PAM-3 Encoding
AnandTech Transmit
000 -1 -1
001 -1 0
010 -1 1
011 0 -1
100 0 1
101 1 -1
110 1 0
111 1 1
Unused 0 0

When we compare NRZ to PAM-3 and PAM-4, we can see the rate of data transfer for PAM-3 is in the middle of NRZ and PAM-4. The reason why PAM-3 is being used in this case is to achieve that higher bandwidth without the extra limitations that PAM-4 requires to be enabled. 

NRZ vs PAM-3 vs PAM4
AnandTech Bits Cycles Bits Per
NRZ 1 1 1
PAM-3 3 2 1.5
PAM-4 2 1 2

PAM-3 has similar limitations to NRZ.

The final line on this image is ‘[something] N6 test-chip focusing on the new PHY technology is working in [the lab and] showing promising results’. That first word I thought was TSMC, but it has to be about the same width as the ‘The’ on the line above. So it doesn’t look like I’m right there, but N6 is a TSMC node.

Intel’s goal with Thunderbolt is going to be both driving bandwidth, power, and utility, but also right now it seems keeping it to the USB-C standard is going to be a vital part of keeping the technology useful for users who can fall back on standard USB-C connections. Right now Intel’s TB4 is a superset that includes USB4, so we might see another situation where TB5 is ready to be a superset of USB5 as well, however it seems that USB standards are slower to roll out than TB standards right now.

Special thanks to David Schor from WikiChip for the tipoff.

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  • zhang297 - Monday, August 2, 2021 - link

    PAM3 can carry more than 1.5 bit info per clock if longer encoding sequences are used.
  • TomWomack - Monday, August 2, 2021 - link

    But not very much more - you can't get 1.6 - and 'seven trits to send eleven bits' or 'twelve trits to send nineteen bits' don't fit well with the tendency of bits to come in powers of two.
  • 5j3rul3 - Monday, August 2, 2021 - link

    PCIe 5.0 X2 ?
    Hope Thunderbolt 5 can run as PCIe 5.0 X4 + PD 240W + DP2.0
  • mode_13h - Tuesday, August 3, 2021 - link

    That might depend on how short, inflexible, and expensive you want the cables to be.

    Not to mention the cost of devices supporting it.
  • vladx - Sunday, August 8, 2021 - link

    Yeah, there's no coincidence that both Thunderbolt 5 and Displayport 2.0 have the same bandwidth. It's either intended or Displayport forced their hand.
  • Wuety06 - Monday, August 2, 2021 - link

    So is this basically a new play on differential signaling where you create a 3rd state and hope u can still filter the noise or am I missing something here?
  • mode_13h - Monday, August 2, 2021 - link

    Curious what the maximum length & cost will be, for a passive TB5 cable @ full bandwidth.
  • yeeeeman - Monday, August 2, 2021 - link

    well, i guess now they should just do the right thing and announce TB5 and meteor lake.
  • AnTech - Monday, August 2, 2021 - link

    We have been fooled by Intel too many times now (products that do not deliver to promises like Optane Xpoint, microprocessors delayed for ever, etc). It is just smoke to increase share prices.
  • WaltC - Monday, August 2, 2021 - link

    Yes--nothing matters except the products you can ship--shipping products are the best PR any company can have. It's exactly why Intel is sucking hind teat atm...;)

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