Foundries started limited usage of extreme ultraviolet (EUV) lithography for high-volume manufacturing (HVM) of chips in 2019. At the time, ASML's Twinscan NXE scanners were good enough for production, but the full EUV ecosystem was not quite there. One of the things that impacted EUV was the lack of protective pellicles for photomasks, which limited usage of EUV tools and affected yields. Fortunately, the situation with pellicles has finally improved thanks to the recent introduction of production-ready EUV pellicles, and matters promise to get even better in the coming years.

Protecting Precious Reticles

ASML has made a great progress with its Twinscan NXE EUV lithography tools in the recent years, improving performance of light source, availability time, and productivity. Its industry peers have also done a lot to make high-volume manufacturing (HVM) using EUV equipment possible. Still, the EUV ecosystem needs to develop further. One of the most notorious challenges the semiconductor supply chain faced with EUV is development of pellicles that were not available two years ago, which is why TSMC and Samsung Foundry had to invent ways how to use their EUV scanners without protective films.

For Reference: A 16nm TSMC Pellicle With Reticle

Pellicles protect 6×6-inch photomasks (reticles) during the chip production flow by sealing them away from particles that could land on their surface, which would otherwise damage them or introduce defects to wafers in production. Each reticle for an EUV tool costs $300,000, so chipmakers are eager to protect them against damage by particles or even the EUV radiation itself as this lowers their costs. Meanwhile, reducing risks associated with yields is perhaps even more important.

The need for pellicles, in turn, varies depending on the manufacturer and the types of photomasks employed. Intel, which is known for its big CPU dies, tends to use single-die reticles, which means that just one mask defect introduced by a particle automatically kills the whole die. Meanwhile, if a 25-die photomask is used, a particle adder will 'only' result in 4% lower yield (one dead die), which is why it's been possible to get away without pellicles for smaller chips and multi-die photomasks.

ASML Leading the Pack. For Now

The industry started to develop protective films for EUV tools relatively late after it transpired that nobody can guarantee that an ultra-complex EUV scanner is 100% free of harmful particles, which is why they were not ready in 2019.

Pellicles for photomasks to be used with deep ultraviolet (DUV) lithography equipment are common and cheap. By contrast, since photomasks for EUV are different from photomasks for DUV (EUV masks are essentially 250 to 350-nm thick stacks featuring 40 to 50 alternating layers of silicon and molybdenum on a substrate), pellicles for such reticles are also quite different. In particular, the very short wavelength of EUV means that pellicles for it have a number of requirements that make them uneasy to produce and expensive. EUV pellicles have to be extremely thin, should not affect reflection characteristics of reticles, should feature a high transmission rate (the higher the rate, the higher is productivity of a scanner), should sustain high EUV power levels, and withstand extreme temperatures (from 600ºC to 1,000ºC in the future).

ASML's EUV Pellicle (Image Credit: Semiconductor Engineering)

"Most materials absorb very strongly at the more energetic 13.5nm EUV wavelength and, even when the most EUV-transparent materials are selected, the membranes must be extremely thin to approach 90% transmittance," said Emily Gallagher, a principal member of technical staff at Imec. "Such thin membranes are not usually capable of maintaining sufficient strength to be free-standing at the required dimensions. Additionally, the EUV scanner environment is not compatible with many materials and will subject the pellicle to pump-vent cycles."

To date, a number of EUV pellicle options have emerged, according to SemiEngineering:

  • ASML introduced its first EUV pellicles in 2019 and licensed the technology to Mitsui Chemicals, which intends to start their volume sales in Q2 2021. Since then, ASML has improved its pellicles.
  • Imec has disclosed test results of its pellicles based on carbon nanotubes.
  • Graphene Square, Freudenberg Sealing Technologies (FST), and some universities are developing their own pellicles.

So far, only ASML has managed to create commercially viable pellicles for EUV tools that are actually available. ASML's pellicles are based on polysilicon that is 50 nm thick. Back in 2016, they demonstrated a 78% transmissions rate on a simulated 175W source. Currently ASML can sell a pellicle with an 88% transmission rate. And shortly, Mitsui will start supplying such pellicles in volume.

ASML's latest prototypes made of metal silicide demonstrate a 90.6% transmission rate with 0.2% non-uniformities and less than 0.005% reflectivity on a 400W source.

"This upgrade supports our roadmap, which eventually will take source power up to 400 Watts," said Raymond Maas, ASML’s product manager for pellicles, in an interview with Bits& "The pellicle heats up to 600ºC at that power level, which the polysilicon couldn’t withstand."

By contrast, Imec's prototype pellicles have a transmission rate of 97.7%. In fact, in the long term, when more advanced light sources are available, more sophisticated pellicles will be needed and this is where Imec's carbon nanotubes-based pellicles will come into play.

"Few materials have the potential of high EUV transmission beyond 90% and even fewer materials are at the same time compatible with EUV powers beyond 600W. In addition, the pellicle needs to be strong to be suspended over a large area of the mask (~110mm x 140mm)," said Joost Bekaert, a researcher from Imec.

Unfortunately, it is unclear when Imec's carbon nanotube-based pellicles will be ready for primetime.


TSMC and Samsung Foundry have invented ways to use EUV lithography tools without pellicles on multi-die photomasks for smaller chips, but such methods are risky as any particle adder can become a yield killing defect. Furthermore, such methods are risky for bigger chips and single-die photomasks, so pellicles are critical for enabling large dies to be made with EUV tools. That said, regardless of the photomask size, pellicles are needed to improve EUV yields and reduce risks across the board.

Overall then, the use of and improvements in EUV pellicles will be a gradual process. The initial pellicles developed and made by ASML and soon to be made by Mitsui are good enough for some of today's needs, but there is room for improvement with their transmission levels, as evidenced by the next-generation prototypes developed by ASML and Imec. Better pellicles will be needed to account for future scanners as well, since those machines will have more powerful sources. Nonetheless, since such pellicles have a number of indisputable advantages, they are going to be used by chipmakers as they can help to improve yields even at the cost of some productivity.

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  • ballsystemlord - Wednesday, March 31, 2021 - link

    Here it is:
  • watersb - Thursday, April 1, 2021 - link

    Cool, thanks for the link!

    Here also is an often-cited talk from 2012 by Anders Gofas on fab tech, "Indistinguishable from Magic"
  • basroil - Thursday, April 1, 2021 - link

    Process hasn't really changed all that much from the micron scale days. It's basically just mask, dope, clean, mask,deposit, clean, mask, etch, clean, and repeat , just that the number of layers are increased, mask resolution increased, and doping/deposit materials are newer. Other than using smaller wavelengths and more exotic deposit and dope materials, equipment is pretty much unchanged from 20 years ago.
  • ballsystemlord - Thursday, April 1, 2021 - link

    Do you say this as someone who works in the field or is this just your perspective from 10,000ft?

    I ask this because I've heard talks by people (e.g. Forrest Norrod), who know what goes into CPUs these days and they indicate that things have changed significantly (at least at the transistor level, if not in the fabrication process and materials themselves), to enable CPUs to get up to the GHz speeds that they do.
  • Arsenica - Thursday, April 1, 2021 - link

    In a very basic sense the processes remain similar but as soon as you get to any detailed analysis it no longer holds true.

    For example the Chemical Vapor Deposition processes from the 80´s are only in a superficial sense similar to the Atomic Layer Deposition processes of today.
  • basroil - Friday, April 2, 2021 - link

    "Do you say this as someone who works in the field or is this just your perspective from 10,000ft?"
    Third option: someone who works on the equipment used by fabs. You'll never hear from someone that actually works at a fab engineering department since fab secrecy is usually more important than yields or broken machines, but I've been to both fabs and equipment manufacturers in the US and Asia.

    You would be surprised how the old the design age is on an average piece of hardware even in a 7nm fab, 28nm and older processes typically run exclusively on devices that have components that went end of life decades ago (Intel's 386 processor is a pretty prime example that is extensively used throughout the industry for industrial PC controller boards, last one was taped out in the mid 2000s, yet even 7nm fabs use machines that run on those chips)
  • ballsystemlord - Friday, April 2, 2021 - link

    Wow! Thanks!
  • Lux88 - Thursday, April 1, 2021 - link

    How much time does it take from clean silicon wafer to raw chip (without package) for a DDR4 chip and latest Snapdragon SoC? A day? 4 days? 2 weeks?
  • eastcoast_pete - Thursday, April 1, 2021 - link

    According to the damages supposedly caused by power outages at various foundries, can be several weeks. Modern chips have have multiple layers, and go through many (I believe up to and over 50) coating, exposure, etching and wash/rinse cycles. That's why these power outages are so bad; you basically also have to toss the wafers that were close to their last cycle, which apparently can be three weeks in from the start.
  • FullmetalTitan - Thursday, April 1, 2021 - link

    Turn around times for memory are weeks (3-6, depending on how many stacked layers there are), and for SoC parts it is more like 3 months plus whatever delays in testing and packaging add to it.

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