One of the key metrics on how well a semiconductor process is developing is looking at its quantitative chip yield – or rather, its defect density. A manufacturing process that has fewer defects per given unit area will produce more known good silicon than one that has more defects, and the goal of any foundry process is to minimize that defect rate over time. This will give the customers better throughput when making orders, and the foundry aims to balance that with the cost of improving the manufacturing process.

The measure used for defect density is the number of defects per square centimeter. Anything below 0.5/cm2 is usually a good metric, and we’ve seen TSMC pull some really interesting numbers, such as 0.09 defects per square centimetre on its N7 process node only three quarters after high volume manufacturing started, as was announced in November at the VLSI Symposium 2019. As it stands, the defect rate of a new process node is often compared to what the defect rate was for the previous node at the same time in development. As a result, we got this graph from TSMC’s Technology Symposium this week:

As it stands, the current N5 process from TSMC has a lower defect density than N7 did at the same time in its development cycle. TSMC. This slide from TSMC was showcased near the start of the event, and a more detailed graph was given later in the day:

This plot is linear, rather than the logarithmic curve of the first plot. This means that TSMC’s N5 process currently sits around 0.10 to 0.11 defects per square centimeter, and the company expects to go below 0.10 as high volume manufacturing ramps into next quarter.

Part of what makes 5nm yield slightly better is perhaps down to the increasing use of Extreme UltraViolet (EUV) technology, which reduces the total number of manufacturing steps. Each step is a potential chance to decrease yield, so by replacing 4 steps of DUV for 1 step of EUV, it eliminates some of that defect rate.

TSMC’s first 5nm process, called N5, is currently in high volume production. The first products built on N5 are expected to be smartphone processors for handsets due later this year.

Related Reading

Comments Locked


View All Comments

  • Anymoore - Wednesday, August 26, 2020 - link

    They leveraged the N7 status, so if it's the same D0 they offer no improvement with lower mask count.
  • Anymoore - Wednesday, August 26, 2020 - link

    N5 starts off much better than N7, but is approaching the same level of defectivity. It suggests new issues came up.
  • SaberKOG91 - Wednesday, August 26, 2020 - link

    That's the wrong way to look at it. Defect density is defects per unit area. TSMC has shown a 45% reduction in area for N5 vs N7. That means the number of defects relative to the number of transistors is actually ~1/2 that compared to N7 at the same density. So it's more that ~0.1 is the floor for some other reason. It may simply be that TSMC actually have set 0.1 as their acceptable target and don't push hard on it after the fact, focusing more on power and area improvements to get meaningful gains in performance. You have to factor in the diminishing returns of pumping more money into R&D for only a small improvement in yields vs getting the next process out the door. Meanwhile, most customers are just happy to have double the transistor budget or double the yields per wafer, along-side the improvements in power and/or frequency, compared to the old node.
  • Anymoore - Wednesday, August 26, 2020 - link

    Defect density of N7 got to the same level of defect density in 3Q, N5 is at about the same level in same time. It's the same issue?
  • SaberKOG91 - Wednesday, August 26, 2020 - link

    No. These plots look like classic diminishing returns. Even their prediction line for N5 doesn't show significant improvement in the future. It's far more likely that they have a very rigorous internal schedule with predictable process maturity. Once it gets to a certain point internally they begin ramping production. It probably takes about 9-12 months on average after that point to dial in the process to these kinds of defect densities, at which point they stop trying to make significant improvements and focus on higher wafer throughput instead. TSMC has maintained that they saw much better yields on N5 out of the gate than N7. This just means they were able to start ramping earlier than they expected (ie. starting their 3-4Q long process tuning). I don't think they actually hit any significant issues that stopped them improving, just that it's "good enough" for mass production and any further improvements are expensive to make and pull resources away from the next process node. It's more important that they get the current process churning out wafers and get the next process moving along than it is to keep chasing defect density. They realized a long time ago that smaller feature size more than makes up for not chasing higher yields. Like I said, N5 at the same defect density at N7 has a much lower defect rate for the same transistor budget.
  • Anymoore - Wednesday, August 26, 2020 - link

    The two plots are obviously inconsistent, what is TSMC pulling. Linear vs log is not the explanation.
  • SaberKOG91 - Wednesday, August 26, 2020 - link

    They are consistent. The first plot starts at -2Q, the second starts at -3Q. They added N10 in the second plot which had much higher defect density. This changes the linear scale limits (mainly maximum) for the Y-axis.
  • Anymoore - Thursday, August 27, 2020 - link

    The upper graph shows N5 curving upward toward N7, approaching convergence, while the lower graph shows it maintaining ~80%.
  • Spunjji - Thursday, August 27, 2020 - link

    The second graph is literally just a zoomed-in segment of the first with a trend line and y-axis labelling added in.

    When you say "approaching convergence", that's just a guess - there's no way to know from the information they have provided whether the lines will converge or remain separate. They're predicting the latter, but then they would. So 🤷‍♂️
  • phdthesiswrite - Thursday, August 27, 2020 - link

    Amazing one!thanks for sharing

Log in

Don't have an account? Sign up now