Samsung Foundry this week announced that it has completed development of its first-generation 5 nm fabrication process (previously dubbed 5LPE). The manufacturing technology uses extreme ultraviolet lithography (EUVL) and is set to provide significant performance, power, and area advantages when compared to Samsung’s 7 nm process (known as 7LPP). Meanwhile, Samsung stresses that IP developed for 7LPP can be also used for chips to be made using 5LPE.

5LPE Is Ready (For Sampling)

Samsung’s 5 nm technology continues to use FinFET transistors, but with a new standard cell architecture as well as a mix of DUV and EUV step-and-scan systems. When compared to 7LPP, Samsung says that their 5LPE fabrication process will enable chip developers to reduce power consumption by 20% or improve performance by 10%. Furthermore, the company promises an increase in logic area efficiency of up to 25%.

Advertised PPA Improvements of New Process Technologies
Data announced by companies during conference calls, press briefings and in press releases
vs 28LPP
vs 14LPE
vs 14LPP
vs 10LPE
vs 10LPE
Power 60% 40% 30% ~15% ? 50% 20%
Performance 40% 27% >10% ~10% ? 20% 10%
Area Reduction 50% 30% 30% none ? 40% <20%

The contract maker of semiconductors says that it can reuse all existing 7LPP intellectual property on chips designed for 5LPE technology, which will reduce customers' migration costs and shrink product development cycle. Meanwhile, typically IP vendors tend to optimize and verify their IP for new process nodes, so it remains to be seen whether always reusing 7LPP IP blocks for 5LPE chips will be the most optimal solution.

Samsung Foundry said that it has offered 5LPE process design kit (PDK), design methodologies (DM), electronic design automation (EDA) tools, and IP, to its customers since the Q4 of 2018. In addition, the company has started to provide 5LPE multi project wafer (MPW) shuttle service to its clients. Overall, the technology is ready for design starts and sampling, though it should be noted that as is usually the case with these kinds of announcements, risk production and volume production will still be some distance off.

“In successful completion of our 5nm development, we’ve proven our capabilities in EUV-based nodes,” said Charlie Bae, Executive Vice President of Foundry Business at Samsung Electronics. “Considering the various benefits including PPA and IP, Samsung’s EUV-based advanced nodes are expected to be in high demand for new and innovative applications such as 5G, artificial intelligence (AI), high performance computing (HPC), and automotive.”

EUV Ramping Up at Samsung

In addition to announcing its 5 nm process technology, Samsung Foundry this week shared some details concerning the ramp up of its 7LPP production using EUVL tools. As it turns out, the company had provided commercial samples of 7LPP chips to interested parties and initiated mass production of select designs early this year.

Samsung Foundry Lithography Roadmap, HVM Start
Data announced by company during conference calls, press briefings and in press releases
2017 2018 2019 2020 2021 2022 2022+
1H 2H 1H 2H 1H 2H 1H 2H
*Exact timing not announced
**May be available only to Samsung LSI

As reported, Samsung currently uses ASML’s Twinscan NXE:3400B EUVL scanners to produce 7LPP chips at its Fab S3 in Hwaseong, South Korea. The company is on track to complete its dedicated EUV line in Hwaseong in the second half of 2019 and then start volume production there in 2020.

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Source: Samsung Foundry

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  • saratoga4 - Saturday, April 20, 2019 - link

    Seeing as the foundries' customers are high level engineers with advanced degrees in semiconductors, I really don't think you need to be waiting for regulators to come in and protect them from being fooled. Anyone making decisions about what fab to use is well aware of how big transistors really are.

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