It’s no secret that Intel’s enterprise processor platform has been stretched in recent generations. Compared to the competition, Intel is chasing its multi-die strategy while relying on a manufacturing platform that hasn’t offered the best in the market. That being said, Intel is quoting more shipments of its latest Xeon products in December than AMD shipped in all of 2021, and the company is launching the next generation Sapphire Rapids Xeon Scalable platform later in 2022. Beyond Sapphire Rapids has been somewhat under the hood, with minor leaks here and there, but today Intel is lifting the lid on that roadmap.

State of Play Today

Currently in the market is Intel’s Ice Lake 3rd Generation Xeon Scalable platform, built on Intel’s 10nm process node with up to 40 Sunny Cove cores. The die is large, around 660 mm2, and in our benchmarks we saw a sizeable generational uplift in performance compared to the 2nd Generation Xeon offering. The response to Ice Lake Xeon has been mixed, given the competition in the market, but Intel has forged ahead by leveraging a more complete platform coupled with FPGAs, memory, storage, networking, and its unique accelerator offerings. Datacenter revenues, depending on the quarter you look at, are either up or down based on how customers are digesting their current processor inventories (as stated by CEO Pat Gelsinger).

That being said, Intel has put a large amount of effort into discussing its 4th Generation Xeon Scalable platform, Sapphire Rapids. For example, we already know that it will be using >1600 mm2 of silicon for the highest core count solutions, with four tiles connected with Intel’s embedded bridge technology. The chip will have eight 64-bit memory channels of DDR5, support for PCIe 5.0, as well as most of the CXL 1.1 specification. New matrix extensions also come into play, along with data streaming accelerators, quick assist technology, all built on the latest P-core designs currently present in the Alder Lake desktop platform, albeit optimized for datacenter use (which typically means AVX512 support and bigger caches). We already know that versions of Sapphire Rapids will be available with HBM memory, and the first customer for those chips will be the Aurora supercomputer at Argonne National Labs, coupled with the new Ponte Vecchio high-performance compute accelerator.

The launch of Sapphire Rapids is significantly later than originally envisioned several years ago, but we expect to see the hardware widely available during 2022, built on Intel 7 process node technology.

Next Generation Xeon Scalable

Looking beyond Sapphire Rapids, Intel is finally putting materials into the public to showcase what is coming up on the roadmap. After Sapphire Rapids, we will have a platform compatible Emerald Rapids Xeon Scalable product, also built on Intel 7, in 2023. Given the naming conventions, Emerald Rapids is likely to be the 5th Generation.

Emerald Rapids (EMR), as with some other platform updates, is expected to capture the low hanging fruit from the Sapphire Rapids design to improve performance, as well as updates from the manufacturing. With platform compatibility, it means Emerald will have the same support when it comes to PCIe lanes, CPU-to-CPU connectivity, DRAM, CXL, and other IO features. We’re likely to see updated accelerators too. Exactly what the silicon will look like however is still an unknown. As we’re still new in Intel’s tiled product portfolio, there’s a good chance it will be similar to Sapphire Rapids, but it could equally be something new, such as what Intel has planned for the generation after.

After Emerald Rapids is where Intel’s roadmap takes on a new highway. We’re going to see a diversification in Intel’s strategy on a number of levels.

Starting at the top is Granite Rapids (GNR), built entirely of Intel’s performance cores, on an Intel 3 process node for launch in 2024. Previously Granite Rapids had been on roadmaps as an Intel 4 node product, however, Intel has stated to us that the progression of the technology as well as the timeline of where it will come into play makes it better to put Granite on that Intel 3 node. Intel 3 is meant to be Intel’s second-generation EUV node after Intel 4, and we expect the design rules to be very similar between the two, so it’s not that much of a jump from one to the other we suspect.

Granite Rapids will be a tiled architecture, just as before, but it will also feature a bifurcated strategy in its tiles: it will have separate IO tiles and separate core tiles, rather than a unified design like Sapphire Rapids. Intel hasn’t disclosed how they will be connected, but the idea here is that the IO tile(s) can contain all the memory channels, PCIe lanes, and other functionality while the core tiles can be focused purely on performance. Yes, it sounds like what Intel’s competition is doing today, but ultimately it’s the right thing to do.

Granite Rapids will share a platform with Intel’s new product line, which starts with Sierra Forest (SRF) which is also on Intel 3. This new product line will be built from datacenter optimized E-cores, which we’re familiar with from Intel’s current Alder Lake consumer portfolio. The E-cores in Sierra Forest will be a future generation than the Gracemont E-cores we have today, but the idea here is to provide a product that focuses more on core density rather than outright core performance. This allows them to run at lower voltages and parallelize, assuming the memory bandwidth and interconnect can keep up.

Sierra Forest will be using the same IO die as Granite Rapids. The two will share a platform – we assume in this instance this means they will be socket compatible – so we expect to see the same DDR and PCIe configurations for both. If Intel’s numbering scheme continues, GNR and SRF will be Xeon Scalable 6th Generation products. Intel stated to us in our briefing that the product portfolio currently offered by Ice Lake Xeon products will be covered and extended by a mix of GNR and SRF Xeons based on customer requirements. Both GNR and SRF are expected to have full global availability when launched.

The E-core Sierra Forest focused on core density will end up being compared to AMD’s equivalent, which for Zen4c will be called Bergamo – AMD might have a Zen5 equivalent when SRF comes to market.

I asked Intel whether the move to GNR+SRF on one unified platform means the generation after will be a unique platform, or whether it will retain the two-generation retention that customers like. I was told that it would be ideal to maintain platform compatibility across the generations, although as these are planned out, it depends on timing and where new technologies need to be integrated. The earliest industry estimates (beyond CPU) for PCIe 6.0 are in the 2026 timeframe, and DDR6 is more like 2029, so unless there are more memory channels to add it’s likely we’re going to see parity between 6th and 7th Gen Xeon.

My other question to Intel was about Hybrid CPU designs – if Intel was now going to make P-core tiles and E-core tiles, what’s stopping a combined product with both? Intel stated that their customers prefer uni-core designs in this market as the needs from customer to customer differ. If one customer prefers an 80/20 split on P-cores to E-cores, there’s another customer that prefers a 20/80 split. Having a wide array of products for each different ratio doesn’t make sense, and customers already investigating this are finding out that the software works better with a homogeneous arrangement, instead split at the system level, rather than the socket level. So we’re not likely to see hybrid Xeons any time soon. (Ian: Which is a good thing.)

I did ask about the unified IO die - giving the same P-core only and E-core only Xeons the same number of memory channels and I/O lanes might not be optimal for either scenario. Intel didn’t really have a good answer here, aside from the fact that building them both into the same platform helped customers synergize non-returnable development costs across both CPUs, regardless of the one they used. I didn’t ask at the time, but we could see the door open to more Xeon-D-like scenarios with different IO configurations for smaller deployments, but we’re talking products that are 2-3+ years away at this point.

Xeon Scalable Generations
Date AnandTech Codename Abbr. Max
Node Socket
Q3 2017 1st Skylake SKL 28 14nm LGA 3647
Q2 2019 2nd Cascade Lake CXL 28 14nm LGA 3647
Q2 2020 3rd Cooper Lake CPL 28 14nm LGA 4189
Q2 2021 Ice Lake ICL 40 10nm LGA 4189
2022 4th Sapphire Rapids SPR * Intel 7 LGA 4677
2023 5th Emerald Rapids EMR ? Intel 7 **
2024 6th Granite Rapids GNR ? Intel 3 ?
Sierra Forest SRF ? Intel 3
>2024 7th Next-Gen P ? ? ? ?
Next-Gen E
* Estimate is 56 cores
** Estimate is LGA4677

For both Granite Rapids and Sierra Forest, Intel is already working with key ‘definition customers’ for microarchitecture and platform development, testing, and deployment. More details to come, especially as we move through Sapphire and Emerald Rapids during this year and next.

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  • mode_13h - Monday, February 21, 2022 - link

    > Xeon D is a dud.

    I'd suggest that's specific to the Sky Lake update of Xeon D. I think the Broadwell generation did rather well. Intel merely forgot one of the key ingredients that made it good: power-efficiency.

    So, it's plausible there could be an E-core based equivalent in the future. However, it's equally plausible that some of the ongoing Atom product lines are already growing into the niches where Xeon D was initially successful (e.g. power-constrained edge servers for things like cellular base stations).
  • Mike Bruzzone - Tuesday, February 22, 2022 - link

    mode_13th, Atom into base station. I monitor for industrial embedded Atom in the channel and they don't exist and Atom sales at Tremont / Jasper into consumer markets are way down from prior generations. What does spark "at the edge" for "cell base stations" is ARM up against x86. ARM has two network infrastructure fronts. One from the edge up and one from core; data center, down network 'head end' infrastructure . . . building a railroad from two end points toward middle.

    At Avoton, Rangely followed by and Denverton were meant to quash ARM incursion at the edge and did not. ARM owns cell base station.

  • mode_13h - Wednesday, February 23, 2022 - link

    > Atom sales at Tremont / Jasper into consumer markets are way down from prior generations.

    I presume that's because they're low-margin products. So, Intel is de-prioritizing them, given that it's constrained on the supply-side.

    Also, I can tell you that other component shortages are making life hard for OEMs and ODMs. There might be less "pull" for these CPUs from their end, if they're having to divert what components they can get towards *their* higher-margin products. Also, because when you *can* get components in short supply, the prices are inflated - making lower-margin products much less profitable (if at all).
  • Oxford Guy - Saturday, February 19, 2022 - link

    That motherboard photo shows how unserious enterprise is about performance. Notice how the RAM boards have no tall aggressive-looking spreaders, nor rhinestone designs, nor RGB.
  • Oxford Guy - Saturday, February 19, 2022 - link

    And I bet there’s no skull on the storage. Truly unfortunate that so much performance is being left on the table.
  • JayNor - Saturday, February 19, 2022 - link

    "Yes, it sounds like what Intel’s competition is doing today, but ultimately it’s the right thing to do"

    I think it would be a step in the wrong direction. Their Foveros base IO tile seems a better solution for the future than the non-scalable sprawling distance between io tile and compute tiles.
  • whatthe123 - Sunday, February 20, 2022 - link

    they're still using foveros when the bandwidth is required like their aurora gpu. having an IOD is pretty much required to avoid the design flaw of sapphire rapids where they had to mirror features on every die. sapphire rapids approach may end up faster for memory access but it makes it difficult to scale up and down the stack.
  • Rοb - Saturday, February 19, 2022 - link

    The Intel LGA 4677 is going up against AMD's LGA 6096, while many of the pins will be for power the other half *must do something*. It's probably future-proofing for PCIe 6 and additional DDR6 channels.

    It's nice to know that the socket will last a few extra generations, if that's the takeaway.
  • schujj07 - Sunday, February 20, 2022 - link

    AMD is also going 12 channel DDR5 for Rent Epyc. Intel is only going to be 8 channel DDR5. Once again Intel didn't put RAM density into their decision making for their newest servers. I wonder if after SPR they will go to 12 channel or will the be late to the game again like they were with 8 channel.
  • schujj07 - Sunday, February 20, 2022 - link

    Further note on RAM density. When virtualizing, RAM is your biggest constraint when it comes to number of VMs that can be run on a host. While hypervisors do RAM compression, ballooning, and other things to allow the over allocation of RAM, performance drops very quickly across all VMs on the host once RAM over allocation happens. I've seen performance tank to the point of applications failing at a 10% RAM over allocation. The hosts I manage are all dual socket 32c/64t Epyc Rome's with 1TB RAM. I could easily add more VMs to each host if I had extra RAM. I'm at a steady state 10-15% CPU usage and 50% RAM usage. The mose popular DIMMS are 64GB for DDR4. Zen4 will give me 768GB/socket (1DPC) vs 512GB for Intel. This is why RAM density is so important for virtualization and Intel is behind again.

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