JEDEC still has not published the DDR5 specification officially, yet it looks like DRAM makers and SoC designers are preparing for the DDR5 launch at full steam. Cadence, which was vocal about the new technology back in 2018, and has since released provisional DDR5 IP (the DDR5 controller and PHY) commercially, this week presented some additional information about the upcoming DDR5 market release as well as the technology's progress.

DDR5 Platforms Getting Ready

On the SoC side of matters, we already know that AMD’s EPYC ‘Genoa’ as well as Intel’s Xeon Scalable ‘Sapphire Rapids’ will support DDR5 DRAM when they launch in the 2021 ~ 2022 timeframe. What is noteworthy, is that Cadence’s provisional DDR5 IP has ‘over a dozen design-ins’, so there are over 12 SoCs supporting DDR5 in various stages of development right now. Some of these system-on-chips will come earlier and some will be available later, but it is evident that there is a serious interest towards the technology among developers of SoCs.

Cadence is confident that its DDR5 controller and PHY are compliant to the formal JEDEC specification, so SoCs that use its IP will be compatible with upcoming DDR5 memory modules.

Cadence's DDR5 testboard with a module on it

Here is what Marc Greenberg, director of DRAM IP marketing at Cadence, said:

“Close participation in the JEDEC working groups is an advantage. We get insight into how the standard will develop. We are a controller and PHY vendor and can anticipate any potential changes on the way to final standardization. In the early days of the standardization, we were able to adopt standard elements under development and work together with our partners to get very early working silicon. As we approach the release of the standard, we get more proof points to indicate that our IP will support DDR5 devices compliant to the standard.”

For Starters: 16 Gb DDR5-4800

Transition to DDR5 represents a major challenge for DRAM makers because the chips are set to increase capacity, rise data transfer rates, increase effective performance (per clock and per channel), and lower power consumption all at the same time (read more here and here). In addition, DDR5 is expected to make it easier to stack multiple DRAM devices, which will allow to increase DRAM capacity in servers (from what we have today).

Micron and SK Hynix have already announced sampling to partners of their DDR5 memory modules based on their 16 Gb chips. Samsung has not formally confirmed any sampling, but we know from its ISSCC 2019 announcement that the company has been preparing and evaluating its 16 Gb DDR5 devices and modules on internally for a while now. Anyhow, DDR5 will likely be available at launch from all three major DRAM producers.

Cadence is confident that DDR5 ramp will begin with 16 Gb DRAMs at 4800 MT/sec/pin data transfer rate (something that was indirectly confirmed by SK Hynix’s DDR5-4800 module showcase at CES 2020). From there, DDR5 will evolve in two directions: capacity and performance. Capacity wise, DDR5 will grow to 24 Gb (so expect DDR5 modules of odd capacity like 24 GB, 48 GB, etc.) and then to 32 Gb. As for performance, Cadence expects DDR5 to evolve to 5200 MT/sec/pin data rate in 12 – 18 months after DDR4-4800 launch and then to 5600 MT/s in another 12 – 18 months, so performance progress of DDR5 in servers will occur in a pretty much regular cadence.

On the client side, a lot will depend on controllers and memory module vendors, but enthusiast-grade DIMMs will certainly be faster than those used in servers.

Mr. Greenberg, said the following:

“DDR4 went to 3200 just this year. Adoption of DDR speed grades happens quite slowly. DDR5 is the next step. It is a big leap in bit rate performance. But it will then hang there for 12-18 months, then go up to 5200, and 5600 after that. We are back on the treadmill of one speed grade every 12-18 months.”

In fact, the step from DDR4-3200 to DDR5-4800 will bring a huge performance bump, but it does not end there for servers. Because of 16 Gb chips, internal DDR5 architecture optimizations, new server architectures, and usage of RDIMMs instead of LRDIMMs, single-socket systems with 256 GB DDR5 modules will get a nice performance increase in terms of latency (vs. today’s LRDIMMs).

Here is what Mr. Greenberg said:

“A lot of these machines have 8 channels on a processor [socket], each [channel] with 512 GB, making a 4 TB memory machine where you can access any byte in under 100 ns. If a database index is 4 TB, you can imagine how big a database could be supported. Quite a beast.”

Keeping in mind that AMD’s EPYC ‘Rome’ CPUs already have eight memory channels and support up to 4 TB of DDR4 DRAM per socket using 256 GB RDIMMs, one can take advantage of low latency (vs. LRDIMMs) even today, but not at DDR5’s speeds. Meanwhile, systems with LRDIMM support can have up to 4.5 TB per socket, but at a cost of additional latency.

DDR5 Shipping This Year?

As noted above, AMD’s Genoa and Intel’s Sapphire Rapids are not due until very late 2021, or rather early 2022, but Cadence seems to be optimistic and believes that ‘2020 will be the year of DDR5’. From Cadence’s perspective, this might mean tapeouts of actual DDR5-supporting SoCs (which is about time), but the company’s internal analysis shows that it expects DRAM vendors to actually start shipments of DDR5 memory this year.

Memory makers tend to start volume shipments of new types of DRAM ahead of general availability of platforms. Meanwhile, shipping a year before AMD’s Genoa and Intel’s Sapphire Rapids seems a bit early, but has several reasonable explanations: AMD’s and Intel’s DDR5-supporting processors are closer than communicated by the two companies, there are DDR5-supporting SoCs that are coming to market well ahead of those from AMD and Intel, system makers need time to test DDR5 modules and stock them ahead of major product launches.

In any case, if the DDR5 specification is at the Final Draft stage, it is possible for major DRAM makers to kick off volume production even without a published standard. Theoretically, SoC developers can also send their designs to manufacturing at this stage. Meanwhile, it is hard to imagine DDR5 to capture any sizeable market share in 2020 – 2021 timeframe without support from the major CPU vendors.

Related Reading:

Source: Cadence

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  • dotjaz - Saturday, March 28, 2020 - link

    You do realise none of this make sense apart from the APU part, right? Zen 2 and above are DRAM agnostic.

    AMD will have the IO die (and AM5) with DDR5 ready when the market is ready and pair it with the Zen X module. It's very much feasible to have Zen 3 with current IO die at first next year then by then end of the year, an updated version with a new DDR5 IO die and AM5. They might even do it with Zen 4 to give AM4 platform one last upgrade.
  • FreckledTrout - Monday, March 30, 2020 - link

    AMD has said more than once Zen3 is AM4 so yes for sure it is not using DDR5 for Zen3. For Zen4 that is where the rumor mill comes in and its very likely they will be using DDR5 since AMD is moving to a new socket with Zen4. However they could use DDR4 for Zen4 but have enough pins in the socket to switch over to DDR5 for Zen5 and not have to change sockets.
  • DanNeely - Saturday, March 28, 2020 - link

    Is the others category in the graph primarily GDDR/HBM ram, or something else?
  • watzupken - Monday, March 30, 2020 - link

    At this stage, I actually don't find DDR5 exciting from a retail user standpoint. At a frequency of 4800, high end DDR4 are already there despite consuming more power. Also, I am expecting a steep increase in the latency just to bump the speed up, which somewhat negates the benefit of the speed bump. Historically, latency have crept from low single digits to now mid to high 10s from DDR to now DDR4.
  • BushLin - Monday, March 30, 2020 - link

    Err... Looking at decent, mainstream, non-overvolted RAM over time:
    400Mhz DDR CL2 - 10ns
    500Mhz DDR CL2.5 - 10ns
    800Mhz DDR2 CL4 - 10ns
    1066Mhz DDR2 CL5 - 9.38ns
    1600Mhz DDR3 CL8 - 10ns
    2133Mhz DDR3 CL10 - 9.38ns
    3200Mhz DDR4 CL16 - 10ms
    3600Mhz DDR4 CL18 - 10ms

    When was it dramatically better than 10ns?
  • Spunjji - Tuesday, March 31, 2020 - link

    You've picked some of the higher numbers for each memory speed. DDR2 started at 533Mhz, DDR3 started off at 1066 and most official support ended at 1600Mhz. DDR4 official support started at 2133 and is now at 3200.

    I think your overall point still stands, though. While there hasn't been much of an improvement in latency, the degradation isn't that marked, either - and some things do just need more bandwidth.
  • BushLin - Tuesday, March 31, 2020 - link

    All correct except there not being any worsening of latency. I spent too much time compiling the list to add pointless upgrades where previous generations offered the same/similar speed at worse latency.
    My point is that most considered purchases of RAM remain at around 10ns latency.
    What has changed during this period is improved controllers, which generally have delivered lower effective latencies in spite of this pattern while obviously allowing much higher bandwidth.
  • BushLin - Tuesday, March 31, 2020 - link

    "...where previous generations offered the same/similar speed at worse latency"
    Better latency that should read (can't edit).
    i.e. at the time, getting an X38/X48 chipset with DDR3 1066Mhz CL7 rather than a P45 chipset and DDR2 1066Mhz CL5 made less sense for most (it was also cheaper and allowed a 2166Mhz bus at 1:1 ratio)
    However, Sandy/Ivy bridge was the mature part of the cycle where DDR3 2133Mhz CL9 was cheaper and offered potentially better latency over early DDR4 modules.
    We may well see high speed, sub 10ns DDR4 at good prices before competitive DDR5 comes along.
  • umano - Thursday, April 2, 2020 - link

    Zen 3 promises 10-15 % increase in performance. Considering zen 4 on 5nm process (85% density increase) and DDR5 it will be very hard for zen 3 to make big numbers on the consumer /enthusiast side. I think they need to improve the platform, 10gbe, thunderbolt 4/usb4, and 4/8 pcie lanes more wouldn't be a bad idea. Let's see what will happen

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