GlobalFoundries has introduced its 12LP+ fabrication process that relies on the groundwork set by its 14LPP and 12LP technologies and provides significant improvements when it comes to performance, power, and area (PPA) scaling. The specialty foundry positions the technology for developers of chips for cloud and edge AI applications.

GlobalFoundries’ 12LP+ manufacturing technology builds upon the company’s 12LP process yet enables a 20% increase in performance (at the same power and complexity) or a 40% reduction in power requirements (at the same clocks and complexity) as well as a 15% improvement in logic area scaling when compared to 12LP platform. Among other things, 12LP+ supports 0.5V SRAM bit cells (which probably use IP that the company designed for its 7 nm nodes). In addition, GF developed a new 2.5D interposer that enables 12LP+ SoCs to work with HBM memory.

Advertised PPA Improvements of New Process Technologies
Data announced by companies during conference calls, press briefings and in press releases
vs 12LPP
vs 14LPP
vs 14LPP
GF's 7nm Gen 1
vs 14LPP
Power 40% - ? >60%
Performance 20% 10% ? >40%
Area Reduction 15% 15% ? >50%

The foundry says that its 12LP+ uses a mature design and production ecosystem and provides advantages comparable to those of 7 nm-class fabrication process. Meanwhile, significant improvements and a new PDK point to new design libraries along with numerous new features, which means that GlobalFoundries’ clients will have to make significant investments in order to take advantage of 12LP+. Those investments will still be 50% lower than the cost of transition to a 7 nm-class technology, according to GlobalFoundries.

Michael Mendicino, vice president of Digital Technology Solutions at GF, said the following:

“Our 12LP+ solution already offers clients a majority of the performance and power advantages they would expect to gain from a 7nm process, but their NRE (non-recurring engineering) costs will average only about half as much, a significant savings. Additionally, because the 12 nm node has been running longer and is much more mature, clients will be able to tape-out quickly and take advantage of the growing demand for AI technology.”

To speed up development of 12LP+ chips for its clients, GlobalFoundries has asked Arm to design Arm Artisan physical IP and POP IP required by AI-focused SoCs. That IP is said to be compatible with 12LP. Meanwhile, the 12LP+ PDK is already available and several clients have begun to design chips using the technology. GlobalFoundries expects its customers to tape out the first 12LP+ SoCs sometimes in the second half of 2020 and produce them in volume in 2021.

GlobalFoundries will manufacture 12LP+ chips using deep ultraviolet (DUV) lithography with argon fluoride (ArF) excimer lasers operating on a 193 nm wavelength at its Fab 8 in New York, USA. Presumably, the company will use the same equipment that is currently used to make SoCs at 12LP and 14LPP nodes.

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Source: GlobalFoundries

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  • Hul8 - Thursday, September 26, 2019 - link

    AMD could design their 4000 series APUs (using Zen 2) on this node. Since I/O doesn't scale well to 7nm and this seems cheaper to design (and maybe cheaper to manufacture), the lower cost APUs could be a good fit.
  • scineram - Thursday, September 26, 2019 - link

  • ksec - Wednesday, September 25, 2019 - link

    I think the I/O die is still on 14nm, if it could move to 12nm LP+, that could mean significant reduction in power. Although that die size is still huge even if it could scale down. ( I/O tends to not scale well )
  • Death666Angel - Wednesday, September 25, 2019 - link

    Epyc and TR are 14nm IO die. Ryzen 3000 is 12nm.
  • scineram - Thursday, September 26, 2019 - link

  • Cooe - Thursday, September 26, 2019 - link

    Yes. Maybe use Google first before you "No" something.
  • levizx - Sunday, September 29, 2019 - link

    No to your no
  • JasonMZW20 - Thursday, September 26, 2019 - link

    They're all on 12nm LP. An early engineering sample of Epyc Rome had a 14nm LPP IO die, but has since been moved to 12nm LP for final products.

    Epyc's IO die doesn't need to be any larger than it already is.
  • Rudde - Thursday, September 26, 2019 - link

    Anandtech reported that consumer (Ryzen) products use 12nm LP I/O die, while servers use 14nm LP. I've personally found AMD communication confusing about the matter.
  • levizx - Sunday, September 29, 2019 - link

    Nope, Matisse IO Die is already 12LP

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