While today second quarter earnings report from Intel represented a high-water mark for the company amid booming sales and revenues, unfortunately not everything disclosed today was good news from the company. As part of Intel’s quarterly earnings presentation, the company announced that their under-development 7nm manufacturing process has suffered a six month delay due to a defect in the process. As a result, the first consumer products aren’t due until at least late 2022, leaving Intel with 10nm as their best in-house manufacturing process for the next couple of years.

But even more important than that, the delay has spurred some soul searching within Intel, driving the company to pivot on its manufacturing plans and open the door to using third-party fabs for a much broader segment of its products. Going forward, the company will be taking what CEO Bob Swan and other leadership are calling a “pragmatic” approach, looking at both in-house and third-party fabs and using those fabs that make sense for the company and the product in question. And while the company has not announced any specific plans to outsource production – they are looking at it for products in the 2022-and-later timeframe – it would be hard to overstate how dramatic of a shift this is for the industry, and for a company that even five years ago was the world’s leader in silicon lithography manufacturing.

7nm Delayed By Six Months

But before we get too far into Intel’s future plans, let’s talk about the past and the present, and how those are driving Intel’s decision to look towards outside fabs. Ever since Intel’s 10nm process suffered repeated delays, Intel’s plan to get the company’s manufacturing side back on track was to nail the development of their 7nm process. The goal was to deliver 7nm on time – making up for the time lost from the 10nm delays – getting a solid process out that Intel could quickly ramp up, retaking the lead in the race to sustain Moore’s Law. A side-effect of this plan would have been that 10nm was to be a relatively short-lived process, allowing Intel to get off of the troubled process rather quickly and on to the more reliable 7nm process.

Unfortunately for Intel, developing their 7nm process has not gone to plan. As revealed in today’s call, 7nm yields are roughly a full year behind schedule – that is, Intel expects it to take another year to get yields to where they wanted them for Q2 of 2020. As a result, the company has needed to push back the bulk of its 7nm product schedule by 6 months. The first 7nm client CPUs are now not expected before late 2022 or early 2023. Meanwhile the first 7nm server part is not expected until the first half of 2023.

The only 7nm part that remains (roughly) on schedule at this point is Ponte Vecchio, Intel’s Xe-HPC GPU that will be going into the Aurora supercomputer. That is expected to ship in late 2021 or early 2022, and even then Intel is evaluating whether to move the manufacturing of some of Ponte Vecchio’s parts to third-party fabs.


For Reference: Intel's Fab Schedule Circa May 2019

The good news, at least, is that despite all of this, Intel believes that they have a good grasp on the problem. With Swan describing the problem as a “defect mode” that was reducing yields, Intel has found the root cause of the issue and is moving to fix it, stating that that the company doesn’t believe that there are any fundamental roadblocks in their 7nm process. So as Intel’s current plans go, the company is still all-in on 7nm, and baring further issues, it’s going to become the cornerstone of their technology in 2023 when it begins volume shipping.

None the less, a six month delay is still a six month delay, and it comes at a time when Intel can ill afford it. Intel’s repeated 10nm problems set the company back years, and the ramifications to Intel’s product lines are ongoing as they continue to ship 14nm desktop and server processors. Meanwhile, though not wholly comparable in terms of node size, fab rival TSMC is set to start shipping 5nm parts this year, extending their lead over Intel and giving TSMC’s customers a leg-up in terms of things like power efficiency and die sizes. At the end of the day Intel has already been down this road once before with 10nm, and they’re intent on not repeating the same mistakes.

Being Pragmatic Means Knowing When to Yield

As a result of the 7nm delay, going forward Intel will be taking what Swan is calling a “pragmatic” approach in selecting what foundries to use. Intel will no longer be limiting themselves to near-exclusive use of their own fabs, and instead the company will be taking the capabilities (and costs) of third-party fabs into the equation. At the end of the day Intel still wants to produce market-leading chips, and they are now willing to use third-party fabs to accomplish this.

We will continue to invest in our future process technology roadmap, but we will be pragmatic and objective in deploying the process technology that delivers the most predictability and performance for our customers, whether that be our process, external foundry process or a combination of both.
-Intel CEO Bob Swan

While Intel isn’t committing to any specific manufacturing plans today, the message from Intel is clear: they will do what they need to in order to deliver new products according to their release roadmap. This means relying on third-party fabs as a contingency plan and leaving virtually every option on the table, including manufacturing a product entirely at a third-party fab if that is truly the best option. Ultimately, the question Intel is facing is how much should they rely on their 7nm fabs, and how much should they rely on third parties.

Meanwhile, underpinning this newfound philosophy of flexibility are Intel’s recent developments in what the company is terming “disaggregated die” technologies like EMIB and Foveros. These multi-chip packaging technologies, which have been rolled out in products like Kaby Lake-G and Intel’s new Core-L “Lakefield” processors, allow for multiple dissimilar dies to be used on a single package. In Lakefield’s case, that was accomplished by layering a 10nm compute die on top of a 22nm I/O die, allowing Intel to make the performance critical parts of the chip on the relatively expensive 10nm process, while non-critical parts were built on an extremely power efficient version of 22nm.

Lakefield, in turn, is the first of what will be many products from Intel using this technology. By gluing chips together Intel can not only better manage yield issues – defects are far less disruptive when they impact a small chiplet instead of a large monolithic die – but it means Intel can continue to mix-and-match different process nodes. And not just different Intel process nodes, but third-party process nodes as well.

We’ve already seen a very small taste of this with Kaby Lake-G, which used a GlobalFoundries-built GPU with an Intel-built CPU, albeit on a very coarse scale with minimal integration. But going forward intel’s flexibility plans mean they need to do it on a much larger and finer-grained scale. The upshot is that based on Lakefield there seems to be little doubt Intel can do this – which fab the chips come from shouldn’t have much of an impact on packaging – and instead it’s a question of how much of it Intel does. It’s clear that no matter what, Intel has to go the chiplet route for future products, as chiplets are what will enable Intel’s fab flexibility. But which of those chiplets will be Intel-made, and which of them will be made by third-party fabs? Intel will be spending the next couple of years figuring out just that.

Finally, it bears mentioning that none of this would even be possible without Intel’s other recent pivot towards divorcing product designs from process nodes. The company’s traditional vertically-integrated design philosophy has delivered a lot of excellent products over the years, but Intel has been feeling the pain of this decision since 10nm was delayed, and with it the use of their newer Sunny Cove CPU architecture. Intel has only recently gained the ability to port an architecture to multiple process nodes, and it’s clear they are going to be heavily relying on that ability as part of any third-party chipmaking.

But First, Ponte Vecchio

While the bulk of Intel’s announcement today deals with products set for the 2023 timeframe, the company has also publicly commented on what it means for their very first 7nm product, Ponte Vecchio. The Xe-HPC GPU is the flagship of Intel’s Xe GPU efforts, and Ponte Vecchio chips are a fundamental building block of the forthcoming Aurora Supercomputer. But even more importantly for Intel right now are delivery dates: Aurora is scheduled to be delivered in 2021, a year before Intel is set to deliver their first high-volume consumer 7nm parts. Ponte Vecchio is an extremely important product for Intel, and they only have a limited amount of time left to work on it.

As a result, Intel has confirmed that the company is also reevaluating what fabs are used for the various parts of Ponte. Curiously, Intel has stated that the chip was always going to use a mix of first-party and third-party fabs, though I wonder if Intel is being a bit fast & loose there by including the HBM memory (which Intel doesn’t produce) in that assessment. At any rate, even if you exclude the memory, that still leaves the I/O base die, the connectivity chips, and the GPU itself as separate dies, any of which could theoretically be shuffled off to a third party fab.

To be sure, like the other announcements today Intel is sharing their specific manufacturing plans – and it’s likely Intel hasn’t even made a final decision on where to make the various chips. But at the same time Intel is making it clear that they are considering all of their options. The Aurora supercomputer was already scrapped once (when it was planned to be a Xeon Phi system), so Uncle Sam is going to be eager to get his $500M supercomputer, and Intel in turn may need to swallow some of its pride to make it happen.

Many Unknowns, but Intel’s Transformation Is Certain

Wrapping things up, while there are a lot of unknowns and things left to be determined in Intel’s plan, there is one thing that is certain: no matter what happens, Intel will be transforming. At a minimum they will be transforming from a company that relies on monolithic dies to a company that embraces multi-chip packages, and depending on how things go with 7nm, they may also be transforming into a company that farms out much of its chip production to third parties. This is nothing short of a remarkable change for a company that ruled the world of chipmaking not even half a decade ago.

But it’s a remarkable change that needs to happen. Though undoubtedly a hard pill for Intel to swallow, Intel’s 7nm delay poses a significant risk to a company that is already bracing for hard times from their 10nm delay. So something needed to change, if only so that Intel has a contingency plan in place should 7nm slip yet again.

At the end of the day what happens next is still up in the air. Intel has decisions to make, and perhaps most importantly of all, Intel’s process technology team is facing a do-or-die situation with 7nm. Intel has invested a great deal in their 7nm process, and for both profit and product reasons, they would certainly prefer to use that. This means that if Intel can keep 7nm on track, then what is now just a contingency plan will likely remain just that.

But regardless of what happens, it’s clear that Intel can no longer bet the house on themselves. Silicon lithography is only getting harder, and a very mortal Intel has to prepare for the possibility that it's a race they may not win.

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  • peevee - Friday, July 24, 2020 - link

    Do you think with the prices like that they are not customized for every client?
  • Santoval - Saturday, July 25, 2020 - link

    What do you mean by "customize"? Optimize for TSMC or, er, "unoptimize" for Intel? The former might be an option, with the potential input or even active contribution of TSMC. The latter makes no sense though. Even if Intel wanted to"unoptimize" their EUV scanners out of sheer incompetence ASML would point out that what they want or ask would cause them this or that issue. Therefore I strongly doubt Intel's issue is with their EUV step-and-scan machines.
    Also bear in mind that Intel are not using EUV at all for their 10nm node. It is entirely DUV based with SAQP printing. Intel's 7nm parts are their first (production) parts with any EUV layers.
  • Speedfriend - Sunday, July 26, 2020 - link

    If you know anything about an EUV machine, you will know that physically is is not customised. It is the single most complex piece of machinery ever made
  • HomelessHardware - Sunday, July 26, 2020 - link

    Questions:
    1) if both tsmc and Intc are using the same machines, why can one push out 7nm and the other cannot? Is Intc adding more complication to their design?

    2) shouldn’t ASML help Intc fix whatever issues there are so they don’t lose the second biggest fan in the world?
  • Spunjji - Wednesday, July 29, 2020 - link

    Put simply: there's a lot more to a silicon manufacturing process than just the lithography machines.

    ASML aren't involved in those parts of the process. I'm not sure they *could* help.
  • serpretetsky - Friday, July 24, 2020 - link

    I believe 7nm is Intels' EUV process. I dont know how dependant their 7nm EUV is on 10nm. It might not have any of the same problems as 10nm (probably a bunch of different problems though), and they probably have separate parallel teams working on it. If that is the case then there isn't as much incentive to necessarily get 10nm done as soon as possible. 7nm is just as important if not more so.
  • Lolimaster - Saturday, July 25, 2020 - link

    Because even dumbed down their 10nm is still broken and unfixable.
  • Gondalf - Saturday, July 25, 2020 - link

    Hard times for AMD.
    A big contract with Intel means nearly zero 5nm silicon for AMD.
  • Spunjji - Wednesday, July 29, 2020 - link

    Gondalf posting FUD as per usual. Guess who already has orders down for the 5nm process before Intel even began considering this? I'd give you a list, but it's shorter just to say: not Intel. 😂
  • Santoval - Saturday, July 25, 2020 - link

    "Intel should concentrate on 10nm for the time being, why talk so much about 7nm when it's in such dire straits?"
    Because Intel's 10nm node is a fundamentally flawed node. It is also highly complex, even for today, and that complexity in turn leads to lower yields and thus higher costs and lower profit margins. In particular it is too complex for DUV lithography with SAQP printing. It should be OK with EUV (and maybe SADP), but EUV was not ready when Intel started developing their 10nm node (even today it's not 100% ready).

    Intel had a lot of trouble in particular with their switch to cobalt (from copper) of the two lowest layers (M0 & M1) of their metal stack and their introduction of COAG (Contact Over Active Gate). I heard they were thinking of ditching one of them in their + and ++ node variants, but I can't recall which one.

    They also decided to relax the transistor density of their highest density 10nm cell variant* in these subsequent node variants, in an effort to increase yields and drive down costs, even if that means slightly larger dies. I strongly doubt they have ever released anything with that quoted ~101 million transistors per mm^2 density except, perhaps, that poor Cannon Lake i3 they have been trying to forget. Even that was clearly not fully fabbed at the 10nm node's highest density, since that would make no sense. Perhaps the only Intel part that *was* fully fabbed at that node if the 10nm logic die of Lakefield, since that would increase its energy efficiency.

    *Intel's 10nm node is employed in *three* different cells, ranging in density from 67 MTr/mm^2 (highest performance - lowest density, with 12 fins) to 101 MTr/mm^2 (lowest performance - highest density, with 8 fins). All three cells are used for different parts of the same processor, depending on the best fit of each. In other words the quoted ~101 MTr/mm^2 transistor density of Intel's 10nm node is largely a marketing fabrication (which is "not even wrong", except it really is). That density is only used in cells for things like IO and uncore parts, *not* for the CPU and iGPU cores, which require the lowest density (with the possible exception of Lakefield). More in the link below.
    https://www.anandtech.com/show/13405/intel-10nm-ca...

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